Until recently, accepting longer runtimes was their only option. They simply don’t have the money and manpower to provide enough on-site compute resources to ensure reliability verification runtimes that can keep a design on schedule. Many design companies must confront budget and resource issues on a regular basis. 1,2,3 However, the rapid and substantial growth in the number and complexity of reliability checks has introduced a new limitation-the availability of sufficient compute resources. Time is of the essence, and automated reliability verification is now a non-negotiable component of tapeout.įortunately, with the advent of foundry reliability rule decks, EDA companies have been able to provide automated reliability verification tools and checks to support design companies. Designers no longer have the luxury of hand-checking critical paths. 1), achieving reliability goals has never been harder. Product performance and expected life are essential to market success, but as elements like electrostatic discharge (ESD) and latch-up protection become more complex ( Fig. Sound familiar? While that scenario may ring true for all IC verification flows, reliability verification can be particularly at risk. Deadlines are in peril, as you see business opportunities slipping away. Design rules become more complicated, requiring more checks that take longer to run. Effects that were nominal at previous nodes suddenly become critical. With each process node, integrated-circuit (IC) designs get more complex.
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